This invention relates to a high-speed LSI system, more particularly to a high-speed data transfer system for a computer processor LSI system having peripheral LSIs, memory chips or the like with memory control capability, and I/O control capability or the like.
For realizing a high-performance computer it is important both to increase the speed of the processor LSIs and to speed up data transfer among the LSIs constituting the computer. One method available for increasing transfer speed is that in which the data are transmitted at a pitch which is shorter than the propagation time. A clock signal generation method for realizing this transfer method is taught, for example, by Japanese Laid-Open Patent Public Disclosure 62(1987)-204359 (Synchronized data transfer system). Japanese Laid-Open Patent Public Disclosure 2(1990)-226316 (Semiconductor device) discloses another clock signal generation method. Other publications disclosing a similar purpose include Japanese Laid-Open Patent Public Disclosures 62(1987)-263561, 63(1988)68959, 2(1990)-201567, 3(1991)-257650 and 4(1992)-84354.